SMIC 65nm LL Standard analog IO
Key Features
- Standard digital IO;
- Cell Size (Width * height) 55um * 135um with DUP in-line bonding pads;
- Work voltage: 2.5V power with 3.3V input tolerance; 3.3V power with 5V input tolerance;
- SMIC 0.065?m Logic Salicide 1.2V/2.5V low leakage Process;
- Suitable for 7 layers application (double top metal);
Technical Specifications
Foundry, Node
SMIC 65nm LL
Maturity
In Production
SMIC
In Production:
65nm
LL
Related IPs
- SMIC 65nm LL 3.3V-2.5/1.2V Power Regulator
- CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad.
- DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration - 40nm LL
- Single Wire Protocol (SWP) Master Analog Front End (AFE) compliant with the ETSI 102.613 standard
- Single Wire Protocol (SWP) Slave Analog Front End (AFE) compliant with the ETSI 102.613 standard
- SMIC 55nm LL Standard analog IO