SMIC 55nm LL ESD protection cell

Key Features

  • Local ESD protection cell for 1.2V device, 1.8V device, 2.5V device and 3.3V device in core area;
  • Cell Size (Width * height) 70um * 55um; 70um * 85um or 35um * 123um;
  • Work voltage: 1.2V/1.8V/2.5V/3.3V power;
  • SMIC 55nm Logic Salicide 1.2/1.8/2.5/3.3V Low Leakage Process;
  • Metal uses M1~M3;

Technical Specifications

Foundry, Node
SMIC 55nm LL
Maturity
In Production
SMIC
In Production: 55nm LL
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Semiconductor IP