SMIC18LL_VDD33SW_01, a 3.3V switchable power control block also called 3.3V power bypass control
block, is developed by VeriSilicon and has been optimized for Semiconductor Manufacturing
International Corporation (SMIC) 0.18¦Ìm low leakage 1.8/3.3V Logic 1P4M Salicide process. This block
includes a 3.3V input and a 3.3V output with one bypass enable control pin (1.8V signal, high true). It can
provide a maximum 100mA output driving current.
SMIC 0.18um Low Leakage Process
Overview
Key Features
- Process: SMIC 0.18um low leakage 1.8V/3.3V 1P4M logic process
- Input voltage: 3.0v~3.6v
- Output voltage: VIN-0.15~VIN when the supply voltage VIN is between 3.0V~3.6V
- Maximum output current: 100mA
- IO type: two inline bonding pads, one for 3.3V input and the other for 3.3V output
- Cell area: 184um *253um
- Operating temperature: -40¡ãC~+25¡ãC~+125¡ãC
- Robust ESD performance: HBM-2KV and MM-200V
- Other: Easy interface with VeriSilicon SMIC 0.18um process standard I/O libraries
Technical Specifications
Foundry, Node
SMIC 0.18um
Maturity
GDS Ready
Availability
Now
SMIC
Pre-Silicon:
180nm
EEPROM
,
180nm
G
,
180nm
LL
Related IPs
- SMIC 0.18um Low Leakage 9 track Standard Cell Library,1.8v operating voltage
- GSMC 0.18um Ultra Low Leakage 9track Standard Cell Library, 1.8v operating voltage
- Analog I/O - low capacitance, low leakage
- Foundation IPs at SMIC 40LL Process
- ECO Library IPs at SMIC 40LL Process
- ECO Library IPs at SMIC 40ULP Process