SmartCard (IEC7816) Synthesizable Transactor

Overview

Key Features

• Adherent to ISO/IEC 7816-3 Specification
• Supports complete IEC7816-3 Tx/Rx functionality
• Supports complete SmartCard and SIM Card commands supported
• Supports all functions for complete smart card sessions, including
• Card activation and deactivation
• Cold/warm reset
• Answer to Reset (ATR) response reception
• Data transfers to and from the card
• Supports adjustable clock rate and bit (baud) rate
• Supports configurable automatic byte repetition
• Supports commonly used communication protocols
• T=0 for asynchronous half-duplex character transmission, and
• T=1 for asynchronous half-duplex block transmission
• Supports Sleep mode and Clock stop mode
• Supports automatic convention detection
• Supports automatic voltage class selection
• Supports configurable timing functions
• Smart card activation time
• Guard time
• Timeout timers
• Supports all three resynchronization levels for the Interface device of the transmission protocol
• Retransmission of blocks
• Use of S(RESYNCH request)
• Warm reset or deactivation
• Supports all three resynchronization levels for the Card of the transmission protocol
• Retransmission of blocks
• Use of S(RESYNCH response)
• Without action by the interface device, the card becomes unresponsive
• Supports all types of error insertion and detection
• Character parity error(s)
• Redundancy code error
• Invalid PCB
• Invalid LEN
• Loss of synchronization
• Failure to receive the relevant S(response) after having transmitted S(request)
• Supports some common SmartCard device model
• Supports both synchronous and asynchronous mode of communication
• Supports both type of CRC poly
• ISO/IEC 13239, or ISO/IEC 14443-3 type B, or ITU-T Rec. V.42
• CRC-T1 as used by many ISO/IEC 7816-3 readers
• Slave/Card BFM supports some standard SmartCard and SIM Card chips

Benefits

• Compatible with testbench writing using SmartDV'S VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

Block Diagram

Deliverables

• Synthesizable transactors
• Complete regression suite containing all the SmartCard (IEC7816) testcases
• Examples showing how to connect and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and functions used in verification env
• Documentation also contains User's Guide and Release notes

Technical Specifications