The Cadence® Verification IP (VIP) for SAS is part of Cadence’s broad storage interface verification IP (VIP) portfolio. Serial Attached SCSI (SAS) has been the interface of choice for mission-critical enterprise storage subsystems, with the next-generation SAS 24G addressing the transmission and storage of data growing at an exponential rate due to an increasingly connected world. As a part of Cadence’s datacenter and cloud solution, the VIP for SAS delivers a comprehensive solution that was delivered ahead of the 2017 SAS plug-festival. Built on top of an industry-known and proven platform that was designed for easy integration in testbenches at the IP, system-on-chip (SoC), and system level, the SAS VIP runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce time spent on environment development, and redirect the saved time to cover a larger verification space, accelerate verification closure, and ensure end-product quality.
The Cadence SAS VIP is a complete verification solution that includes a complete bus functional model (BFM), integrated protocol checks, coverage model, a rich set of error injection capabilities, and compliance tests. Supporting all previous SAS generation data rates (1.5G, 3G, 6G, and 12G) along with all application-level protocols (SSP, SMP, STP), the VIP for SAS allows users to verify all SAS device configurations (initiator, target, and expander). With a layered architecture and powerful callback mechanism, verification engineers can verify SAS features at each functional layer (Phy, link, transport, and application layer) and create highly targeted designs while taking advantage of the latest design methodologies for random testing to cover a larger verification space.
Supported specification: SPL-4 specification.
