IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI Controller IP > MIPI SPMI IP > Simulation VIP for MIPI SPMI

Simulation VIP for MIPI SPMI

Overview

Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI® SPMIsm (System Power Management Interface) protocol. Incorporating the latest protocol updates, the Cadence® Verification IP for SPMI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for SPMI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: MIPI specifications for SPMI v1.0 and v2.0.

Key Features

  • Topology
    • Multiple subordinates and multiple mains topology
  • Clock
    • High Speed and Low Speed device classes
  • Main Connection
    • Main Connection by Detection of SSC, Bus Idle, Bus arbitration
  • Main Arbitration
    • Main Priority and Secondary arbitration requests
  • Subordinate Types
    • RCS and NRCS subordinates
  • Sl Arbitration
    • Supports A-bit and SR-bit subordinate arbitration requests
  • Packet Generation
    • Command, Address, Data, No Response Frame, SPMI commands
  • Device Address Types
    • Supports MID, GSID, USID device addresses
  • ACK/NACK
    • ACK/NACK mechanism as per version 2.0 specification
  • Arbitration Generation
    • Capability to generate simultaneous Arbitration request scenario
  • Error Injection
    • Injection/detection of errors for example parity errors/ noise spike at different arbitration level
  • SSC
    • Generation and detection of SSC (Sequence Start Condition)
  • Event Notification
    • Arbitration win/lost, error detection, command/data/address frame sent, subordinate A/SR bit eligibility status

    Block Diagram

    Simulation VIP for MIPI SPMI Block Diagram

    Technical Specifications

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