IP Catalog > Interface IP Cores > VESA DSC IP > Simulation VIP for DSC

Simulation VIP for DSC

Overview

The Cadence® Verification IP (VIP) for Display Stream Compression (DSC) provides an ability to perform comprehensive verification of DSC-related features of display protocols. This product complements the Cadence VIP for MIPI DSI and VIP for DisplayPort and must be used with one of them. The Cadence VIP for DSC is compatible with all main verification languages (such as Verilog, SystemVerilog, e, VHDL, C, SystemC®, and Vera) and industry-standard methodologies (such as UVM, OVM, and VMM), and runs on all leading simulators. DSI VIP complements the Cadence VIP for MIPI DSI and VIP for DisplayPort.

Supported specification: VESA DSC 1.1, 1.2, and 1.2a.

Key Features

  • DisplayPort
  • DSC Version
    • DSC 1.2a (VBR is not supported by the DP specification)
  • Configuration
    • Discovery, Enabling, Disabling
  • Framing and Compressed Stream Mapping
    • 1, 2, 4, 8, 12, 16, 20, 24 slices per line
  • Picture Parameter Set (PPS) Packet
    • PPS packet header and payload
  • DSC DPCD Fields
    • All DSC related registers are supported
  • PSR in DSC
    • PSR SDP and PSR2 Selective Update in DSC Configuration
  • MIPI DSI-2
  • DSC Version
    • DSC 1.1, DSC 1.2
  • Decoding Process
    • Video encoded frames are decoded by VIP monitor
  • Encoding Process
    • Active Processor VIP generates encoded video frames using DSC algorithm
  • Format of DSI Packets
    • Verifies format correctness of DSI packets related to DSC
  • Content of DSI Packets
    • Verifies content correctness of DSI packets related to DSC

    Block Diagram

    Simulation VIP for DSC Block Diagram

    Technical Specifications

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