First to market with full DDR5 DIMM support.
This Cadence Verification IP (VIP) provides support for the JEDEC DDR5 SDRAM Unbuffered, Registered, and Load-Reduced DIMM Design Specification, the DDR5 UDIMM/RDIMM/LRDIMM standard. It provides a mature, highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model VIP for DDR5 DIMM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.
DDR5 DIMM is the next-generation DIMM specification with improvements in the areas of speed, configurability, reliability, and power saving. It supports speeds up to 4800 speed grade. With redefined Control Word Write, DRAM Mode register write interface, and control word settings like programmable latencies and encoded quad modes, it is more flexible. Guarding of the command forwarded to DRAMs and the RCD Control word writes with optional parity checking and detailed specification for different ways of recovery in the case of parity errors makes this more reliable.
Supported specifications: JEDEC DDR5 SDRAM Rev 1.01, JEDEC DDR5RCD01, and JEDEC DDR5DB01.
