Vendor: Cadence Design Systems, Inc. Category: Protocol Bridge

Simulation VIP for AMBA SWD

The Cadence® Verification IP (VIP) for SWD provides support for the Serial Wire Debug protocol which is part of the Arm® Debug In…

Verification IP View all specifications

Overview

The Cadence® Verification IP (VIP) for SWD provides support for the Serial Wire Debug protocol which is part of the Arm® Debug Interface Specification. It provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms incorporating the latest protocol updates with integrated automatic protocol checks and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for SWD runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specification: SWD v1 and v2 as per Arm Debug Interface specification v6.0 (ADIv6.0).

Key features

  • Serial Wire Debug Port
    • Fully supports SWD-DP functionality as per section B4 of ADIv6.0 specification
  • Serial Wire/JTAG Debug Port
    • Fully supports SWD-related functionality of SWJ-DP as per section B5 of ADIv6.0 specification, including customizable JTAG/SWD switching mechanism
  • Error Injection
    • Ability to inject errors at the single-bit level (Parity, Start bit, Park bit, and so on)

Block Diagram

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Simulation VIP for AMBA SWD
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.

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Frequently asked questions about Protocol Bridge IP cores

What is Simulation VIP for AMBA SWD?

Simulation VIP for AMBA SWD is a Protocol Bridge IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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