SHA-256 Processor

Overview

This core is a fully compliant implementation of the Message Digest Algorithm SHA-2⁵⁶. It computes a 256-bit message digest for messages of up to (264 – 1) bits. Simple, fully synchronous design with low gate count.

The OL_SHA256 core is a fully compliant hardware implementation of the SHA-256 algorithm, suitable for a variety of applications.

The SHA-256 algorithm is an upgraded version of the SHA-1 algorithm and it offers improved security. It operates on message blocks of 512 bits for which a 256-bit (8 x 32-bit words) message digest (hash value) is produced. Corresponding 32-bit words of the hash values from consecutive message blocks are added to each other to form the message of the whole message.

Key Features

FIPS 180-2 compliant.
Suitable for data authentication applications.
Fully synchronous design.
Available as fully functional and synthesizable VHDL or Verilog soft-core.
FPGA netlist available for various devices.

Benefits

FIPS 180-2 compliant.
Suitable for data authentication applications.
Fully synchronous design.
Available as fully functional and synthesizable VHDL or Verilog soft-core.
FPGA netlist available for various devices.

Block Diagram

Applications

Electronic Funds Transfer.
Authenticated Electronic data transfer.
Encrypted data storage.

Technical Specifications

Availability

Now

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