The so_ip_sata2_hctrl is a soft core implementation of SATA host controller as defined in the SATA specification 2.6.
So-Logic's SATA-II Host Controller core is fully compliant with the SATA 2.6 specification, and supports both 1.5 Gbit/s and 3.0 Gbit/s data transfer rates.
SATA-II Host Controller core implements physical, link and transport layers. It can use both RocketIO GTP and GTX transceivers found in Xilinx FPGA devices to implement physical signaling required by the SATA specification. For the interface with the host processor IP core uses standard PATA interface, and for the interface with the DMA engine simple TX and RX transaction interface.
SATA-II Host Controller core is delivered with fully automated testbench and a complete set of tests allowing easy package validation at each stage of SoC design flow.
The design of SATA-II Host Controller core is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset. It operates at 37.5 MHz system clock frequency in case of SATA-I (1.5 Gbit/s data transfer rate) mode and at 75 MHz in case of SATA-II (3.0 Gbit/s data transfer rate) mode.
SATA-II Host Controller core can be evaluated using Xilinx FPGA Evaluation Platforms before purchase. This is achieved by using a time-limited demonstration bit file for Zynq-7000, Artix-7, Kintex-7, Virtax-7, Virtex-6 and Virtex-5 FPGA platforms that allows the user to connect it’s HDD to the SATA-II core and evaluate system performance under different transfer scenarios.
