Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
Overview
The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and USB3.0 Super-Speed Architectures specification. The PHY supports the USB3.0 Super-Speed (5Gbps) and PCI-Express Gen1 (2.5Gbps) and Gen2 (5.0Gbps).
Key Features
- USB3.0 Super-Speed: Universal Serial Bus 3.0 Specification, Revision 1.0
- PCI Express: PCI Express Base Specification, Revision 2.0
- Supports all USB3.0 and PCIE2 power management modes
- Supports PCIE L1 PM substates(L1.1 and L1.2) with CLKREQ#
- Supports 16-bit 250-MHz , and 32-bit 125MHz PIPE interface for USB3.0/PCIE Gen2
- Supports 16-bit 125-MHz , and 32-bit 62.5MHz PIPE interface for PCIE Gen1
- Supports wide range of reference clock, 25M/60M/50M/100M
- Built-in BIST pattern generator and checker with programmable modes for stand-alone tests
- -3.5dB/-6dB de-emphasis at the TX side and programmable CTLE equalization at RX side
Technical Specifications
Short description
Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
Vendor
Vendor Name
Foundry, Node
Samsung, 28nm
Maturity
Silicon proven
Samsung
Silicon Proven:
28nm
FDS