RLDRAM2 Memory Model

Overview

RLDRAM2 Memory Model provides an smart way to verify the RLDRAM2 component of a SOC or a ASIC. The SmartDV's RLDRAM2 memory model is fully compliant with standard RLDRAM2 Specification and provides the following features. Better than Denali Memory Models.

RLDRAM2 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

RLDRAM2 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports RLDRAM2 memory devices from all leading vendors.
Supports 100% of RLDRAM2 protocol standard.
Supports all the RLDRAM2 commands as per the specs.
Supports the following devices.

Supports for 8 internal banks for concurrent operation and maximum bandwidth.
Supports Reduce cycle time (15ns at 533MHZ).
Supports Non multiplexed addresses (address multiplexing option available).
Supports SRAM-type interface.
Supports Programmable READ latency (RL), row cycle time, and burst sequence length.
Supports Balanced READ and WRITE latencies in order to optimize data bus utilization.
Supports Data mask for WRITE commands.
Supports Data valid signal (QVLD).
Supports On-die termination (ODT) RTT.
Supports IEEE 1149.1 compliant JTAG boundary scan.
Supports for full-timing as well as behavioral versions in one model.
Supports for all timing delay ranges in one model: min, typical and max.
Protocol checker fully compliant with RLDRAM2 Specification.
Models, detects and notifies the test bench of significant events such as transactions, warnings, timings and protocol violations.
Constantly monitors RLDRAM2 behavior during simulation.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of RLDRAM2 designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the RLDRAM2 testcases.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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