Real Time Image Rectification for HD pictures up to 1920x1080p60Hz

Overview

The IV-Rect IP implements picture rectification for high resolution images like HD (1280x720p60 or 1920x1080p30). The maximum resolution is 2048x2048.
The throughput of the design is 1 pixel per cycle on 3 components 8bit each (e.g. RGB or YUV444). The rectification process requires 1 frame delay through external SDRAM/DDR. The picture content can be interlaced or progressive video.

Programmable parameters are:
input picture size
output picture size
number of video components
distortion coefficients
rotation matrix
translation matrix
camera matrix

Key Features

RGB/YCC input
Output Resolution up to 2048x2048
Input Resolution unlimited
Radial & tangential distortion correction
Perspective Transformation
Rotation, Cropping, Zoom

Benefits

Real time Rectification for HD video, SW for calibration available.
Can also be used to zoom, rotate, warp, pan, tilt, etc.

Deliverables

Verilog 2001 compatible code
Customized for your application
Integrated to your existing code
Easily interfaced to standard I/O standards
Excellent code and expression coverage
FPGA proven design
Real time demos available
Application support available
HDL Source Licenses

Synthesizable Verilog 2001 RTL* (VHDL option available)
Self checking Verilog Testbench **
VCD dump option
Expected results generator
Simulation script
Test stimuli vectors
Test config vectors
Generic API optional available
Coverage reports
Synthesis script
IP Documentation

Netlist Licenses

For FPGA platforms: XILINX, Lattice, Altera
For ASIC: please ask

Technical Specifications

Maturity

Products with XILINX Virtex2, VirtexPro 2, SPARTAN6

Availability

now

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