Real Time Video Image rotation HD up to 1920x1080p60Hz

Overview

The IV-ROT IP implements a full rotation (0-360°) algorithm for high resolution images like HD (1920x1080p30/ 1920x1080p60). The maximum resolution is 2048x2048.
The throughput of the design is 1 pixel per cycle on 3 components 8bit each (e.g. RGB or YUV444). The rotation process requires about 1 frame delay through external SDRAM/DDR. The picture content can be interlaced or progressive. De-interlacing is recommended (iv-deint)
Programmable parameters are:
- pictures size xy
- rotation base xy
- rotation angle Δω
- rotation size xy
Program parameters changes are applied during vertical blanking. The algorithm requires about 3 full frame storage. Rotation starts when one full picture is written to memory. Processed pixel are directly displayed.

Key Features

Free programmable full
picture rotation (0-360°)
Resolution up to 2048x2048
1pixel per clock throughput
Programmable Angle
inc-Omega = 0.022 °
Programmable Base
x/y = 1pix
Cropping option selectable
Padding options
Rotation Shape (Rectangular, others in 64x64 tiles)
Bandwidth efficient architecture
Low processing delay : ~1 Frame

Benefits

Real time rotation based on single register input value.
Zoom option available (up to 4x)

Deliverables

Verilog 2001 compatible code
Customized for your application
Integrated to your existing code
Easily interfaced to standard I/O standards
Excellent code and expression coverage
FPGA proven design
Real time demos available
Application support available
HDL Source Licenses

Synthesizable Verilog 2001 RTL* (VHDL option available)
Self checking Verilog Testbench **
VCD dump option
Expected results generator
Simulation script
Test stimuli vectors
Test config vectors
Generic API optional available
Coverage reports
Synthesis script
IP Documentation

Netlist Licenses

For FPGA platforms: XILINX, Lattice, Altera
For ASIC: please ask

Technical Specifications

Maturity

Products with XILINX Virtex2, VirtexPro 2, SPARTAN6

Availability

now

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