Ramping 12-bit ADC with Sequencer

Overview

Key Features

• TSMC180 process
• Small Area: 0.21mm^2
• SPI (Serial Peripheral Interface) slave
• -40 to 125 Deg C
• Typical Power 3.3 mW
• Sampling Frequency of 3 Ksps
• Input Voltages 0 ~ 2V single-ended (500uV/DN)
• Input multiplexer and calibration Vs included.
• Signal to Noise and Distortion Ratio: 64db
• ENOB 10.3 bits
• PSRR -60db to 1MHz
• Data Latency 331us (one conversion time)
• Input Impedance Rin/Cin = 48-500ohm / 79pF (Dynamic @ Sampling)
• Differential Nonlinearity DNL +/ - 0.5 LSB
• Integral Nonlinearity INL +/- 15 LSB
• Supply Voltages Vdda 5.0V and Vddd 1.8V
• 8 blocks, 2 samp to 128 ksamp per block.
• ADCmpx: 6 inputs + 3 calibration inputs, variable by block
• 19 other controls variable by block

Block Diagram

Applications

• Sampling Low Frequencies to 1kHz.
• Delivering multiple blocks of samples
• Settings for Inputs & ADC adjustable by block
• When a small silicon area is needed
• When external calibrate/offset adj is feasible

Deliverables

• User Guide
• Characterization Report
• CDL netlist
• Layout in GDS 2 format
• LEF view
• .LIB view
• Verilog model

Technical Specifications