Quad Voice CODEC compliant to ITU-T G.712

Overview

Cologne Chip’s IP core C3-CODEC-G712-4 consists of four voice CODECs for telephony applications in compliance with ITU-T recommendation G.712 or G.711.

Usually the ADC and the DAC in a CODEC need analog parts to be integrated into the chip. In contrast C3-CODEC-G712-4 is fully digital. All needed analog characteristics are moved into a few external resistors and capacitors per CODEC. The analog functionality is connected outside the core to three digital I/O Buffers per CODEC.

The main part of the core area is used for digital filters in the transmit and receive path according to ITU-T recommendation G.712. There are sophisticated digital machines in the frontend of the core to minimize the external component cost. Implementing analog functions into fully digital CMOS circuitries becomes feasible by means of DIGICC, Cologne Chip’s digital approach for IP cores. A patent is pending for this DIGICC technology of Cologne Chip.

Key Features

4 CODECs implemented
Fully digital
Interface data format configurable:

16 bit linear or
8 bit a-law / µ-law according to ITU-T recommendation G.711

Performance of the filters according to ITU-T recommendation G.712
Implementable in any CMOS process technology
Implementable also into FPGA with external buffer
Only 3 digital I/O pins needed for each CODEC
Only a few resistors and capacitors required as external components
The signal to total distortion complies to ITU-T recommendation G.712
Suppression of 50 Hz and 60 Hz in the ADC better than 45 dB
Separate gains for transmit paths (ADC) and receive paths (DAC) for each CODEC programmable
Power reduction to nearby zero in stand-by mode possible
8 kSample/s or 16 kSample/s internal data configurable for 3.1 kHz or 7 kHz audio bandwidth
Clock frequency: 24.576 MHz
Area: approx. 60k logic gates + RAM
RAM: 4 synchronous, single port RAM blocks (128x32bit + 64x32bit + 64x16bit + 32x16bit = 7.68kbit)
Core version with only three, two or one CODEC available (reducing by one CODEC decreases the core by 6k logic gates and 1.92 kbit RAM)

Benefits

Fully digital
Implementable in any CMOS process technology
Implementable also into FPGA with external buffer
Only 3 digital I/O pins needed for each CODEC
Only a few resistors and capacitors required as external components
easy to integrate into all IC designs

Deliverables

Compiled netlist for destination technology, test vectors and behavioral models.

Technical Specifications

Availability

available

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