The second generation Quad-Data-Rate (QDRII) Static Random Access Memory (SRAM) Controller is a general purpose memory controller that interfaces with industry standard QDRII and QDRII+ SRAM. The controller can be configured to function in two-word burst or four-word burst modes. It can also be configured to have an 18-bit bus or a 36-bit data bus. The data is transferred on both edges of the clock, doubling the rate of data transfer. Separate read and write data buses again double the data rate.
The QDRII+ IP Core is implemented using both MACO ASIC gates and soft logic in the FPGA array. Since a significant portion of the implementation is in MACO, more of the FPGA Array is left for the user.
Software Requirements
* ispLEVER version 7.0 or later
* MACO design kit
* MACO license file
QDRII + SRAM Controller MACO Core
Overview
Key Features
- Interfaces to industry standard QDRII or QDRII+ SRAM
- Supports QDRII SRAM memory devices operating up to 250MHz
- Supports QDRII+ SRAM memory devices operating up to 375MHz (highest speed grade)
- FPGA can be configured for 18-bit or 36-bit read and write memory data buses (on FPGA, 36-bit or 72-bit data buses)
- Shared address bus can be configured from 17 bits to 20 bits wide
- Programmable burst lengths of two or four
- Maximum read/write blocks of 31 consecutive locations
Block Diagram
Technical Specifications
Related IPs
- ARINC818 controller Transmitter and Receiver IP core
- QDRII SRAM Controller
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- Ultra low power, high-performance DSP / controller RISC core
- DDR-I/II/III CONTROLLER IP CORE
- QDRII+ SRAM Core