QDRII+ SRAM Core
Overview
This Physical Layer core gives you the ability to simultaneously read and write on every rising and falling edge. QDRII+ is a low-latency SRAM-based standard, used in cache coherent systems, data and packet buffering, lookup tables, and other networking applications.
Key Features
- x18, x36 device targets
- Very low latency reads
- 4 and 2 word burst support
- Reliable and predictable transaction times
- Separate read and write busses
- Source code delivery in Verilog
Technical Specifications
Related IPs
- QDRII SRAM Controller
- QDRII + SRAM Controller MACO Core
- SMIC 0.15umLV Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- SMIC 0.13um High-Speed Synchronous Single-Port/Dual-Port SRAM
- Low power, high speed, and high density configurable SRAM