QDR2 Synthesizable Transactor

Overview

Key Features

• Supports 100% of QDR2 protocol standard CY7C1314CV18
• Supports separate independent read and write data ports with concurrent read and write operation
• Supports full data coherency, providing most current data
• Supports synchronous pipeline read with self-timed late write
• Supports registered address, control and data input/output
• Supports QDR (quad data rate) interface on read and write ports
• Supports fixed 4-bit burst for both read and write operation
• Supports two input clocks (K and K) for accurate QDR timing at clock rising edges only
• Supports two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches
• Supports two echo clocks (CQ and CQ) to enhance output data traceability
• Supports single address bus
• Supports byte write function
• Supports simple depth expansion with no data contention
• Supports programmable output impedance
• Supports single multiplexed address input bus latches address inputs for both read and write ports
• Supports separate port selects for depth expansion
• Supports synchronous internally self-timed writes
• QDR II operates with 1.5 cycle read latency when delay lock loop (DLL) is enabled
• Operates similar to a QDR I device with one cycle read latency in DLL off mode
• Supports available in x18, and x36 configurations
• Supports variable drive HSTL output buffers
• Supports all the QDR2 commands as per the specs
• Supports delay lock loop (DLL) for accurate data placement
• Supports full-timing as well as behavioral versions in one model
• Models, detects and notifies the test bench of significant events such as transactions, warnings, and timing protocol violations

Benefits

• Compatible with testbench writing using SmartDV VIP's
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

Block Diagram

Deliverables

• Synthesizable transactors
• Complete regression suite containing all the QDR2 testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and function's used in verification env
• Documentation contains User's Guide and Release notes

Technical Specifications