The programmable CMOS frequency divider is a set of 8 serially connected dividers with the varied dividing ratio 2/3. This structure is especially effective for wide range of dividing ratio since the number of triggers to accomplish the specified ratio is minimized. The dividing ratio is 2…511.
Input frequency is 88...500 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
Programmable 9-bit CMOS frequency divider (2…511 dividing ratio)
Overview
Key Features
- iHP SGB25V
- Range of dividing ratio 2…511
- Maximum input frequency 500 MHz
- Compact structure
- Portable to other technologies (upon request)
Applications
- PLL frequency synthesizer
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
iHP SiGe BiCMOS 0.25 um
Maturity
Pre-silicon verification
Related IPs
- Programmable CMOS frequency divider (32...16383 dividing ratio)
- Programmable 9-bit CMOS low-frequency divider (5...511 dividing ratio)
- Programmable CMOS frequency divider (56..16383 dividing ratio)
- Programmable CMOS HF divider (16…4095 dividing ratio)
- Programmable frequency divider (56 to 16383 dividing ratio)
- Programmable 6-bit CMOS frequency divider