Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application. PMIC is used for switching and LDO regulators. PMIC-I3C Interface used to select suitable power fit for various application environment. PMIC device is intended to operate up to 12.5MHz.
Power Management IC - I3C Basic Interface IP
Overview
Key Features
- Maximum Operating speed 12.5MHz
- Flexible Open Drain IO (I2C) and Push Pull (I3C Basic) IO Support
- Multi Time Programmable Non-Volatile Memory
- Programmable and DIMM specific registers for customization
- Error log registers
- Input and output power good status reporting mechanism
- Packet Error Check (PEC) Function
- Parity Error Check Function
- Bus Reset Function
- I3C Basic mode Supports
- Write Mode
- Read Mode
- Packet Error Code (PEC) Supported
- Default Read Operation
- Support In Band Interrupt (IBI)
- I2C mode Supports write, read and default read operation
- PEC and Parity error Handling
- CCC error Handling
- I3C Basic Common Command Codes (CCC)
- DEVCTRL
- SETHID
- SETAASA
- ENEC
- DISEC
- RSTDAA
- DEVCAP
- GETSTATUS
Block Diagram
Deliverables
- Verilog Source code
- User Guide
- IP Integration Guide
- Simulation Script
- Synthesis Script
- Encrypted UVM Verification Environment
- cocotb Verification Environment
- Basic Testsuite
- Firmware code
Technical Specifications
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- I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus. I3C Basic Specification Design
- MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification