PLL Lock detector with low current consumption and high accuracy

Overview

The lock detector monitors the current status of PLL by comparing the phase difference of VCO divided signal and reference oscillator signal with required value. It is available to set the lock monitoring period and the lock detector accuracy (6...8.7 ns).

Key Features

  • AMS BiCMOS 0.35 um technology
  • Low current consumption
  • High accuracy
  • Portable to other technologies (upon request)

Applications

  • Phase-locked loop synthesizer

Deliverables

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Technical Specifications

Foundry, Node
AMS BiCMOS 0.35 um
Maturity
Silicon proven
Availability
Now
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Semiconductor IP