PLL (Frequency Synthesizer) IP, Input: 10MHz - 50MHz, Output: 10MHz - 200MHz, UMC 40nm LP process
Overview
Input 10-50MHz, output 10-200MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Logic process(Note:same schematic with FXPLL010HH0L, but Poly Density Errors are waived in layout for 40% area reduced.).
Technical Specifications
Short description
PLL (Frequency Synthesizer) IP, Input: 10MHz - 50MHz, Output: 10MHz - 200MHz, UMC 40nm LP process
Vendor
Vendor Name
Foundry, Node
UMC 40nm LP
UMC
Pre-Silicon:
40nm
LP
Related IPs
- PLL (Frequency Synthesizer) IP, Input: 10MHz - 50MHz, Output: 10MHz - 200MHz, UMC 40nm LP process
- PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 10MHz - 200MHz, UMC 0.18um G2 process
- PLL IP, Input: 10MHz - 200MHz, Outout: 50MHz - 1000MHz, UMC 90nm SP process
- PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.11um HS/AE process
- PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 55nm LP process
- PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process