PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 55nm LP process
Overview
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 55nm LP/RVT Low-K Logic process.
Technical Specifications
Foundry, Node
UMC 55nm LP
UMC
Pre-Silicon:
55nm
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