Pipelined Divider
Overview
Function y = a / b is a very high-speed divider with configurable dividend and divisor width. Inputs and outputs may be specified as either signed or unsigned values. Generates the quotient and remainder after division and includes a flag for a divide by zero exception. Fully scalable alternative to using large LUT-based dividers.
Key Features
- Function y = a / b
- Input values as signed or unsigned integers
- Output values as signed or unsigned integers
- Configurable dividend and divisor width
- Quotient, remainder and divide by zero outputs
- High-speed fully pipelined architecture
- Optimization mode for speed/area trade off
- 400MHz+ operation on basic FPGA platforms
- Fully scalable design
Benefits
- Technology independent soft IP Core
- Suitable for FPGA, SoC and ASIC
- Supplied as human-readable source code
- One-time license fee with unlimited use
- Field tested and market proven
- Any custom modification on request
Block Diagram
Applications
- Fundamental unit in digital processing functions
- Division of integers and fixed-point numbers
- Implementation of reciprocal function f(x) = 1/x
Deliverables
- VHDL source-code (or Verilog on request)
- Simulation test bench
- Examples and scripts
- Full pdf datasheet
- One-to-one technical support
- One years warranty and maintenance
Technical Specifications
Foundry, Node
All