The phase-frequency detector (PFD) consists of 2 D-trigger with reset from external circuit, performed in ECL logic and multiplexer, which allow to switch the input signals to the corresponding inputs.
The block is fabricated on AMS BiCMOS 0.35 um technology.
Phase-frequency detector in ECL logic
Overview
Key Features
- AMS BiCMOS 0.35 um
- Differential structure
- Ability to work with VCOs with both positive and negative frequency dependence of the control voltage
- Input frequencies up to 100MHz
- Only-up/only-down test modes
- External reset circuit
- Documentation
- Portable to other technologies (upon request)
Applications
- Phase-locked loop synthesizer
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
AMS BiCMOS 0.35 um
Maturity
Silicon proven
Availability
Now
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