The phase-frequency detector (PFD) consists of a signal level converter from differential reduced swing ECL to single-ended full swing CMOS signal and two D-flip-flops with reset, made in CMOS logic. Multiplexer allows to switch the input signals to the corresponding inputs.
The block is fabricated on AMS BiCMOS 0.35 um technology.
Phase-frequency detector in CMOS logic
Overview
Key Features
- AMS BiCMOS 0.35 um
- Ability to work with VCOs with both positive and negative frequency dependence of the control voltage
- Input frequencies up to 100 MHz
- Differential CMOS output signal
- CMOS output signal for lock detector
- Built-in reset delay circuit
- Portable to other technologies (upon request)
Applications
- Phase-locked loop synthesizer
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
AMS BiCMOS 0.35 um
Maturity
Silicon proven
Availability
Now
Related IPs
- PLL CMOS phase-frequency detector with ECL charge pump
- PLL CMOS phase-frequency detector with CMOS charge pump
- Phase-frequency detector in ECL logic
- PLL ECL phase-frequency detector with ECL charge pump
- 0.1 to 25 MHz Phase-frequency detector with charge pump
- 24.84 MHz Phase-frequency detector with charge pump (input amplitude 150…210 mV)