Peripheral Direct Memory Access Controller

Overview

The CC-PDMA-APB-AHB is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on FPGA and ASIC technologies.

Key Features

  • AMBA APB3 slave bus
  • AMBA AHB-Lite master bus
  • Configurable number of peripheral channels
  • 8, 16, 32 bits data transfer modes
  • Upstream and downstream data aggregation to 32 bit chunks
  • Various address modes
  • Various arbiter priority schemes
  • Circular buffer support
  • Configurable independent upstream and downstream FIFOs
  • Maskable interrupts
  • Dedicated upstream and downstream peripherals DMA interface
  • Fully synthesizable synchronous design with positive edge clocking
  • DFT ready

Benefits

  • Synthesizable RTL Verilog source code
  • Technology independent IP Core
  • Suitable for FPGA and ASIC
  • Silicon and FPGA proven
  • Easy SoC integration
  • Full implementation and maintenance support with individual approach
  • Flexible licensing scheme

Block Diagram

Peripheral Direct Memory Access Controller Block Diagram

Deliverables

  • Verilog RTL source code
  • Verification suite
  • Datasheet and integration guide
  • C-header file
  • Constraints
  • Technical support

Technical Specifications

Availability
Now
UMC
Silicon Proven: 130nm
×
Semiconductor IP