Vendor: PrimeSoC Technologies Category: PCI Express

PCIE Gen6 digital controller (End Point)

PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links.

Overview

PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE specification Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications.

Key features

  • Compliant wiPCIE Gen 6 Spec.
  • Compliant wiPipe 5.X Spec.
  • PrimeSOC’s PCIE Gen 6.O Core supports Flit and non – Flit Mode.
  • Supports X16, X8, X4, X2, X1 Lane Configuration.
  • AXI MM and Streaming supported.
  • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6 modes.
  • Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s.
  • PAM support when operating at 64GT/s
  • 8b/10b,128b/130b,1b/1b encoding , decoding support.
  • Supports serdes and non – serdes architecture.
  • Optional DMA support as plugin module.
  • Support for alternate negotiation protocol.
  • Lane polarity thru register control.
  • Lane deskew supported.
  • Support for L1 states.
  • L0P Supported.
  • SKP OS add/removal.
  • SRIS mode supported.
  • No equalization support thru configuration.
  • Deemphasis negotiation support at 5GT/s.
  • EI inferences in all modes.
  • PTM, OBFF, MSI, MSIX, Power management and all message format supports.

What’s Included?

  • Verilog soft IP
  • Sample testbench

Specifications

Identity

Part Number
PRIMEEXPRESS
Vendor
PrimeSoC Technologies

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about PCI Express IP core

PCI Express Security and TEE Integration, Part 1 - Establishing Trust

Protecting processor memory alone is no longer sufficient. The entire I/O path must become part of the trusted computing architecture. To address this challenge, PCI-SIG® has developed a suite of complementary security technologies, including Data Object Exchange (DOE), Component Measurement and Authentication (CMA), Integrity and Data Encryption (IDE), and the TEE Device Interface Security Protocol (TDISP).

Frequently asked questions about PCIe IP cores

What is PCIE Gen6 digital controller (End Point)?

PCIE Gen6 digital controller (End Point) is a PCI Express IP core from PrimeSoC Technologies listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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