The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 serial bus standard where SRIS (Separate RefClk Independent Spread-spectrum clock generation) is required. This SSCG PLL is designed for digital logic processes and use robust design techniques to work in noisy SoC environments.
The SSCG PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.8V IO devices. Eliminating band-gaps and integrating all on-chip components such as capacitors helps the jitter performance significantly and reduces stand-by power.
SSCG PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 25 100 MHz Output Frequency FOUT 47 1500 MHz Output Duty Cycle tDO 45 55 % Lock Time tLOCK 100 µs Reset Time tRESET 1 µs PLLOUT Output Random Jitter RJO 1 ps-RMS Modulation Frequency FM 30 33 kHz Modulation Depth (down-spread) DMD -0.5 0 % Modulation Depth (center-spread) DMC -0.25 0.25 % Modulation Frequency Slew (see NOTE3) FS 1250 ppm/µs Area (drawn) A 0.091 sq. mm Total Power (unloaded) IDD 16 mW Operational Voltage (Digital) VDIG 0.72 0.8 0.88 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V Operational Temperature TOP -40 25 125 C Table 1: SSCG PLL Operational Range SSCG PLL Functional Specification The phase-locked loop (PLL) block is provided as a drop-in functional block. The PLL accepts input frequencies of 25MHz or 100MHz, and can produce a wide range of output frequencies, as detailed in Table 1.