PCIe 6.0 PHY on 5nm
Overview
The Qualitas' 5nm PCIe PHY IP consists of hardmacro PMA and PCS compliant to PCIe Base 6.0 specification. This IP offers a cost-effective and low-power solution using 5nm FinFet CMOS technology. It includes all ESD I/Os and bump pads, and supports extensive built-in self test features such as loopback and scan.
Key Features
- 5nm low power enhanced (LN05LPE) CMOS device technology
- 1.8V±5%, 0.85V±5% dual power supply
- Compliant to PCIe Base 6.0 and PIPE 6.1 specification
- Support Gen1, Gen2, Gen3, Gen4, Gen5 and Gen6
- Channel Configuration for Data Lanes
- Common (CMN) and 1, 2 or 4 Data Lanes
- Support the following transmitter pre-emphasis levels
- - 3.5/-6dB for Gen1 and Gen2
- Multi-tap FIR with resolution of 1/63 for Gen3 to Gen6
- Support CTLE, DSP-based multi-tap FFE and 1-tap DFE for channel equalization in receiver
- Support adaptive channel equalization
- 100MHz reference clock is required (Support differential input buffer)
- Built-in self test feature capable of generating and checking PRBS patterns
- PCS included in PHY hardmacro
Benefits
- Low power consumption and small area
- Support 1-, 2- and 4- lane configurations
- Automatic built-in self-test (Loopback)
Block Diagram
Applications
- Mobile, Automotive, Storage, AI accelerator and Chip-to-chip interconnect
Deliverables
- FE-Common: MODEL, TWRAP, TB, LEF, LIBERTY, ATPG and Platform_PSI_CMN
- BE-Common: CIR, GDS, DRC, LVS and DFM
- DOC-Common: DataSheet, UserGuide and TestGuide
Technical Specifications
Foundry, Node
Samsung Foundry SF5A
Maturity
DK Ready
Availability
Aug-24
Related IPs
- PCIe 6.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation
- PHY for PCIe 6.0 and CXL for TSMC 5nm FinFet
- PCIe 6.0 PHY, TSMC N6 x4 1.2V, North/South (vertical) poly orientation
- PCIe 6.0 PHY NCS, TSMC N3E x4 1.2V, North/South (vertical) poly orientation
- PCIe 4.0 PHY on 5nm
- PCIe 6.0 PHY G2 , TSMC N5 x2, North/South (vertical) poly orientation