PCIe 4.0 Controller with AXI

Overview

Key Features

• PCI Express layer
  • Comprises complete PCIe 4.0 interface subsystem with Rambus PCIe 4.0 PHY
  • Compliant with the PCI Express 4.0 or 3.1/3.0, and PIPE (8-, 16- and 32-bit) specifications
  • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
  • Supports Endpoint, Root-Port, Dual-mode configurations
  • Supports x16, x8, x4, x2, x1 at 16 GT/s, 8 GT/s, 5 GT/s, 2.5 GT/s speeds
  • Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
  • Supports many ECNs including LTR, L1 PM substates, etc.
• AMBA AXI layer
  • Compliant with the AMBA® AXI™ Protocol Specification (AXI3, AXI4 and AXI4-Lite) and AMBA® 4 AXI4-Stream Protocol Specification
  • Supports multiple, user-selectable AXI interfaces including AXI Master, AXI Slave, AXI Stream
  • Each AXI interface data width independently configurable in 512-, 256-, 128-, and 64-bit
  • Each AXI interface can operate in a separate clock domain
• Data engines
  • Optional built-in Legacy DMA engine
    • Up to 8 DMA channels, Scatter-Gather, descriptor prefetch
    • Completion reordering, interrupt and descriptor reporting
  • Optional Address Translation tables for direct PCIe to AXI and AXI to PCIe communication

Benefits

• 20+ years of experience in design of IP cores for ASIC with specialization in high-speed interface protocols and technologies, more than 6200 customers , including several hundred of ASIC tape-outs
• Silicon target 16 nm FinFET TSMC and 28 nm roadmap
• Configurable user interface with clock-domain-crossing provides maximum interfacing flexibility and throughput.
• Engineered for both ASIC/SoC and FPGA implementations. Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with same RTL. Fully timing closed on leading edge FPGA from Altera and Xilinx.
• Advanced AMBA AXI interconnect enables heterogeneous SoC interfacing. Allows AXI3 and AXI4 peripherals to coexist and communicate efficiently through the interconnect interface.
• Fully configurable communication engine features programmable DMA and Address Translation Windows, allowing flexible and high-performance AXI-to-PCIe, PCIe-to-AXI, and AXI-to-AXI data transfers.
• Smart ordering rules management enables hazards and deadlocks prevention while ensuring optimized traffic flow.
• Configurable error detection and reporting enables application specific error management thus simplifying application software.
• Support for advanced Low Power states enables lower power consumption in energy-conscious applications
• Flexible PCIe interface configuration in endpoint and root port modes. Includes ECAM support for dynamic configuration of the entire PCIe hierarchy from the AXI domain.
• Provided with latency optimized Linux x64 PCIe device driver allowing immediate software development. Driver source code available for custom developments.

Block Diagram

Applications

• HPC,
• Cloud Computing,
• AI,
• Machine Learning,
• Enterprise,
• Networking,
• Automotive,
• AR/VR,
• Test and Measurement

Deliverables

• Verilog RTL,
• Supporting Documentation

Technical Specifications