PCIe 4.0 Controller with AMBA AXI interface

Overview

Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Controller is compliant with the PCI Express 4.0 and 3.1/3.0 specifications, as well as with the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including data path size, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power. Rambus PCIe 4.0 Controller is verified using multiple PCIe VIPs and testsuites, and is proven in production silicon in hundreds of designs using a variety of commercial and proprietary PCIe PHYs. Rambus PCIe 4.0 Controller is the #1 choice for designers requiring enterprise-class features, highest performance, reliability, and scalability.

Key Features

PCIe interface:

Complies with the PCI Express Base 4.0 Specification, Rev 4.0
Supports Endpoint, Root-Port, Dual-mode, Switch
Supports link rate of 2.5, 5.0, 8.0 and 16.0 Gbps per lane.
Supports TL-bypass interface for switch implementations
Supports x16, x8, x4, x2, x1 at Gen4, Gen3, Gen2, Gen1 speeds
Maximum payload size of up to 4KB
Support as all memory, I/O, Configuration, and Message transactions
Supports up to 4 End-End TLP prefixes
1 virtual channel (VC)
Up to 8 functions supported for Endpoint configurations
Receive and Replay buffer size configurable
Transmit buffer can be bypassed
Receive/transmit user Application interface
User clock integrated Clock Domain Crossing to support user-selected frequency at the Application Layer

User Interface

Tx/Rx for data
256-bit data path, user selectable frequency
Sideband interfaces for configuration, debug, monitoring, advanced features
Easy customization with the IP Wizard
User backdoor access to the PCIe Configuration Space
Unused features not implemented in Silicon
Transaction layer can be bypassed

Configuration

Implements Type 0 Configuration space for Endpoint designs
Implement Type 1 Configuration space for Rootport, Switch, and -Bridge designs
Up to 6 BARs plus expansion ROM can be implemented for Endpoints
All I/O and memory windows implemented for Rootport

Advanced features include

Multi-function
Multicast (Endpoint as receiver only)
Advanced Error Reporting (AER) support
Data protection : ECRC generation and check suport
Test port functionality
Data Protection (ECC, ECRC)
End-End TLP prefixes
TLP Processus Hint (TPH)
Optimized Buffer Flush/fill (OBFF)
ASPM and legacy power management
Lane reversal
Atomic operations
SRIOV (up to 64 virtual functions perphysical functions)
Address Translation Service, including Page Request Interface
Alternative Routing Interpretation (ARI) for Rootport, Switch and SR-IOV enabled endpoints only
L1 PM substate with CLKREQ
All Power State and associated logic implemented
Native Active State Power Management L0s and L1 state support
Power Management Event (PME message) and Beacon (Wake-Up) support
MSI (up to 32) and INT message support
MSI-X Capability Support
Latency Tolerance Reporting (LTR)
Optimized Buffer Flush Fill (OBFF)
ID-based Ordering (IDO)
Retimer (extension device) presence detection

PHY Interface

PIPE 4.0 and PIE-8 compliant
16-bit, 32-bit and 64-bit PIPE interface
32bit/250 MHz in Gen3 mode on x1, x4, x8
16-bit mode supported on x1, x4, x8 and x16

Benefits

20+ years of experience in design of IP cores for ASIC with specialization in high-speed interface protocols and technologies, more than 6200 customers , including several hundred of ASIC tape-outs
Silicon target 16 nm FinFET TSMC and 28 nm roadmap
Configurable user interface with clock-domain-crossing provides maximum interfacing flexibility and throughput.
Engineered for both ASIC/SoC and FPGA implementations. Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with same RTL. Fully timing closed on leading edge FPGA from Altera and Xilinx.
Advanced AMBA AXI interconnect enables heterogeneous SoC interfacing. Allows AXI3 and AXI4 peripherals to coexist and communicate efficiently through the interconnect interface.
Fully configurable communication engine features programmable DMA and Address Translation Windows, allowing flexible and high-performance AXI-to-PCIe, PCIe-to-AXI, and AXI-to-AXI data transfers.
Smart ordering rules management enables hazards and deadlocks prevention while ensuring optimized traffic flow.
Configurable error detection and reporting enables application specific error management thus simplifying application software.
Support for advanced Low Power states enables lower power consumption in energy-conscious applications
Flexible PCIe interface configuration in endpoint and root port modes. Includes ECAM support for dynamic configuration of the entire PCIe hierarchy from the AXI domain.
Provided with latency optimized Linux x64 PCIe device driver allowing immediate software development. Driver source code available for custom developments.

Block Diagram

Applications

HPC,
Cloud Computing,
AI,
Machine Learning,
Enterprise,
Networking,
Automotive,
AR/VR,
Test and Measurement

Deliverables

Verilog RTL,
Supporting Documentation

Technical Specifications

Foundry, Node

Any

Maturity

In production

Availability

Available

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