PCIe 2.1 Controller

Overview

The PCIe 2.1 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express (PCIe) 2.1 performance with great design flexibility and ease of integration. It is backward compatible with the PCIe 1.1 specification. A PCIe 2.1 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency connectivity for demanding applications in data center, edge and graphics.

How the PCIe 2.1 Controller Works

The PCIe 2.1 Controller is configurable and scalable IP designed for ASIC and FPGA implementation. It supports the PCIe 2.1/1.1 specifications, as well as the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models.

The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including data path size, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power. The PCIe 2.1 Controller is verified using multiple PCIe VIPs and test suites, and is silicon proven in hundreds of designs in production.

Key Features

PCI Express layer
- Compliant with the PCI Express 2.1/1.1, and PIPE (16- and 32-bit) specifications
- Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
- Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
- Supports x16, x8, x4, x2, x1 at 5 GT/s and 2.5 GT/s speeds
- Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, crosslink, and other optional features
- Additional optional features include OBFF, TPH, ARI, LTR, IDO, L1 PM substates, etc.
User Interface layer
- 256-bit transmit/receive low-latency user interface
- User-selectable Transaction/Application Layer clock frequency
- Sideband signaling for PCIe configuration access, internal status monitoring, debug, and more
- Optional Transaction Layer bypass
Unique Features & Capabilities
- Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
- Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
- Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen2 x8 with same RTL code
- Ultra-low Transmit and Receive latency (excl. PHY)
- Smart buffer management on receive side (Rx Stream) and transmit side (merged Replay/Transmit buffer) enables lower memory footprint
- Optional Transaction Layer bypass allows for customer specific transaction layer and application layer
- Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%

Benefits

20+ years of experience in design of IP cores for ASIC with specialization in high-speed interface protocols and technologies, more than 6400 customers , including several hundred of ASIC tape-outs
Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with same RTL.
Availability for PCIe 4.0 early adopters
Silicon target 16 nm FinFET TSMC and 28 nm roadmap
Integrated in ongoing projects with multiple 16G PHY
Root-port, Endpoint, Dual-mode, Switch in depth flexible configuration
Support for advanced Low Power states enables lower power consumption in energy-conscious applications
Configurable user interface with clock-domain-crossing provides maximum interfacing flexibility and throughput.
Extensive data integrity features provide data protection on entire data path for storage and other data critical applications
Acclaimed global 24/5 support

Block Diagram

Applications

HPC,
Cloud Computing,
AI,
Machine Learning,
Enterprise,
Networking,
Automotive,
AR/VR,
Test and Measurement

Deliverables

Verilog RTL,
Supporting Documentation

Technical Specifications

Foundry, Node

Any

Maturity

In production

Availability

Available

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