PCIe 2.0 PHY in UMC (40nm, 28nm)

Overview

Key Features

• Physical coding sublayer (PCS) block with PIPE interface
• Supports PCIe power management features, including L1 substate
• Power gating for lowest standby power
• Low active power using voltage mode TX with under drive supply options
• The multi-channel PHY macro with single clock and control core for higher density
• Supports both internal and external reference clock inputs
• PIPE bifurcation as well as PHY macro aggregation for x8 and x16 PHY configurations
• Multi-featured transmitter and receiver equalization
• Each lane in a multi-channel PHY macro contains its own pseudo random bit sequencer (PRBS) for internal and external loopbacks, used to verify TX and RX circuitry
• Each channel is fully controllable via the test access port (TAP) and core interface
• The PHY IP is capable of mapping the signal eye, and outputs the signal statistics via JTAG interface

Benefits

• Compliant with the PCI Express 2.1, 1.1, and PIPE specifications
• x1, x2, x4, x8, x16 lane configurations with bifurcation
• PCIe L1 substate power management
• Supports power gating and power island
• Embedded bit error rate tester (BERT) and internal eye monitor
• ATE test vectors for complete, at-speed production testing
• Pseudo random bit sequencer (PRBS) generation and checker
• IEEE 1149.6 AC JTAG Boundry Scan
• Beaconing, receiver detection and electrical idle features
• Supports -40°C to 125°C junction temperatures

Applications

• Desktops, laptops, workstations and servers
• Embedded systems and set-top boxes
• Network switches and routers
• Enterprise computing and storage networks
• Consumer portable devices
• Graphics devices
• Wireless devices

Deliverables

• Verilog models
• Liberty timing views (.lib)
• LEF abstracts (.lef)
• CDL netlist (.cdl)
• GDSII
• ATPG models
• IBIS-AMI models
• HSPICE models for TX and RX
• Documentation

Technical Specifications