PCI-X Arbiter Supporting 66 / 100 / 133MHz

Overview

Key Features

• PCI-X rev 1.0a compliant
• Supports 66/100/133MHz
• Fair arbitration using round robin
• Supports up to 5 masters
• Bus parking on latest selected master
• Hidden arbitration
• Observes arbitration timeout
• Limited to PCIX only master
• Full synchronous design

Benefits

• Arbitration Scheme
• The arbiter uses a round-robin arbitration to select the next master. After reset, master 0 is granted default master. If all masters request the bus at the same time, the order of which the bus grant asserted is 0 => 1 => 2 => 3 => 4 => 0 ...
• Bus Parking
• To prevent bus floating, always one master has to be granted bus ownership. If no master request is pending, the arbiter parks the bus on the last selected master by keeping its respective GNT# asserted.
• Device Arbitration Timeout
• A master requesting the bus must initiate a transaction upon having its grant asserted. If the bus remains idle for more than 15 clock cycles, the arbiter assumes the selected master 'broken'. A broken master can reactivate himself again by removing its bus request and reasserting it again. Broken masters are removed from the regular arbitration process.

Deliverables

• VHDL or Verilog RTL Source Code
• Functional Testbench
• Synthesys Script
• Data Sheet
• User Guide
• Hotline Support by means of phone, fax and e-mail

Technical Specifications