PCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platforms. It has been defined to provide software compatibility with existing PCI drivers and operating systems. Being a packet based serial technology, PCI Express greatly reduces the number of required pins and simplifies board routing and manufacturing. PCI Express is a point-to-point technology, as opposed to the multidrop bus in PCI. Each PCI Express device has the advantage of full duplex communication with its link partner to greatly increase overall system bandwidth. The basic data rate for a single lane is double that of the 32 bit/33 MHz PCI bus. A four lane link has eight times the data rate in each direction of a conventional bus.
Lattice’s PCI Express core provides a x1, x2 or x4 endpoint solution from the electrical SERDES interface to the transaction layer. This solution supports the LatticeECP3™, ECP5™ and ECP5-5G™device families. When used with the LatticeECP3, ECP5 and ECP5-5G family of devices, the PCI Express core is implemented using an extremely economical and high value FPGA platform.
PCI Express Endpoint Core
Overview
Key Features
- 250 MHz Reference Clock Input
- 125 MHz, 16-bit Data Path User Interface
- Creates TLPs without ECRC or Sequence Number during Transmit
- Receives Valid TLPs without Sequence Number during Receive
- Credit Interface for Transmit and Receive and for PH, PD, NPH, NPD, CPLH, CPLD Credit Types
- Higher Layer Control for Link Training and Status State Machine (LTSSM) via Ports
- Access to Select Configuration Sapce Information via Ports
- Compliant to PCI-SIG PCI Express 1.1 Base Specifications
- Jungo Windows/Linux driver support
Block Diagram
Technical Specifications
Related IPs
- Virtex-5 Endpoint Block Plus Wrapper for PCI Express (PCIe)
- Spartan-3 LogiCORE Endpoint PIPE for PCI Express (PCIe)
- Endpoint for Gen1 PCI Express
- Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe)
- PLBv46 Endpoint Bridge for PCI Express
- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro