Path Margin Monitor IP
Overview
Available The Path Margin Monitor (PMM) solution consists of multiple PMM units, a PMM controller, and associated software & EDA automation. PMM IP is a building block for the PMM solution which is also supported by an automated implementation flow from Synopsys. Path selection logic, RTL configuration & generation, connecting to functional and/or test paths, synthesis, implementation, timing validation and path qualification are the key functions addressed by the EDA automation provided. Associated software allows the data generated from the PMM solution to be effectively analyzed and allow precise decisions made based on those insights.
Key Features
- Fine grain delay elements for accurate measurement
- Distributed architecture with low overhead for scan
- Automated EDA flow for efficient implementation, data collection and analytics
Benefits
- Provides visibility of silicon structural health
- Real time reporting for analytics
- Monitor test or functional paths throughout silicon lifecycle
- Optimize silicon performance based on actual margins available
Applications
- Measure Timing Margin of Actual Functional Paths In-Test
Deliverables
- Datasheet
- Configured RTL file
- Testbench with loop back tests
- Timing constraints
- Cdc constraints
- Synthesis constraint
Technical Specifications
Foundry, Node
Advanced Node FinFET
Maturity
Available on Request
Availability
Available
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