Parameterizable ROM Built In Self Test Controller
Key Features
- Fully static, synthesizable ROM BIST
- ROM Structure independent CRC Algorithms
- Master Slave, simultaneous multiple ROM Test
- Optional transparent Bypass Mode (hidden ROM test during scan test)
- Optional Zero Output
- BIST Logic Scan testable
- JTAG controllable
Technical Specifications
Availability
Now
Related IPs
- Parameterizable RAM Built In Self Test
- HBM3 Solution enabling access to HBM3 Controller and HBM3 PHY in TSMC N5 1.2V
- HBM3 Solution enabling access to HBM3 Controller in TSMC N5 1.2V
- HBM3 V2 Solution enabling access to HBM3 Controller and HBM3 PHY in TSMC N3E
- PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface
- ISA / PC Card / PCMCIA CompactFlash Controller