Parameterizable RAM Built In Self Test
Key Features
- Fully static, synthesizable RAM BIST
- Independent Set of Test Algorithms for Application specific Test Coverage
- RAM Structure independent Algorithms
- Data Retention Rest
- Single Port (1RW) and Dual Port (1R1W, 2RW) Implementations
- Master Slave, simultaneous multiple RAM Test
- Optional transparent Bypass Mode (hidden RAM test during scan test)
- Optional Write Through Test Mode
- Optional Zero Output
- BIST Logic Scan testable
- JTAG controllable
Technical Specifications
Availability
Q4/99
Related IPs
- Parameterizable ROM Built In Self Test Controller
- Embedded Configuration and Test Processor
- 32-bit RISC Processor To Deliver High Performance In Low-Cost Microcontroller Applications
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- Negative Differential Resistance based (NDR-based) RAM Cell
- 26GHz VCO in SiGe