IP Catalog > Interface IP > Telco/OTN IP > OTN IP > OSU/OTN processor, optimized for E1/STM1/OC3/STM4/OC12/FE/GE services over OTU0/OTU1 lines

OSU/OTN processor, optimized for E1/STM1/OC3/STM4/OC12/FE/GE services over OTU0/OTU1 lines

Overview

The TPS3204MP OSU processor is an IP Core solution designed for Xilinx FPGAs. TPS3204MP processors accept 4x STM1/STM4/FE/GE and 4x E1 client signals, process and present them to either OSU or ODU containers for their transport over OTU0/OTU1 bearers. The OTU line signals can be configured in a variety of protection configurations: 1+1, Linear, Ring. TPS3204MP processors support OTU, ODU and OSU signal overheads. For Ethernet client-services, Ethernet bandwidth limiting is provided, along with integrated IEEE 1588 V2 H/W Time Stamping. TPS3204MP processors support hitless bandwidth adjustment of OSU containers carrying Ethernet information. Integrated HDLC controllers can be assigned to GCC in-band communications channels. TPS3204MP processors are offered as complete turn-key solutions, including built-in jitter filters, without necessitating external PLLs.

Key Features

  • Supports NG-OTN
  • 2x OTU0/OTU1 Line-Side OTN
    • Supports G.709 overheads
  • 4x FE/GE/STM1/STM4 and 4x E1 client-services
  • Alarms Monitoring and Performance Counters on lines and client-services
  • Supports the transport of client-services over OSU or ODU containers
  • Supports 1+1 protection
  • Ethernet Rate limiting
  • Supports increasing/decreasing the size of OSU containers transporting Ethernet services
  • IEEE 1588 Precision Timing Protocol H/W time stamping
  • Seamless management of Apodis processors
  • Integrated solution on Xilinx FPGAs:There is no need for external filters
  • Seamless management of Apodis processors
  • SDK (Software Development Kit)
  • Technical Documentation

Block Diagram

OSU/OTN processor, optimized for E1/STM1/OC3/STM4/OC12/FE/GE services over OTU0/OTU1 lines Block Diagram

Technical Specifications

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