IP Catalog > Interface IP > Interconnect IP > Other > OCP Assertion IP

OCP Assertion IP

Overview

OCP Assertion IP provides an efficient and smart way to verify the OCP designs quickly without a testbench. The SmartDV's OCP Assertion IP is fully compliant with standard OCP Specification.

OCP Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

OCP Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • OCP 2.0/2.1/2.2 support
    • All signal level checks including X detection
    • Support transaction and transfer level checks
    • Support for all data and address widths
    • Supports all OCP protocol burst models, burst lengths and response types
    • SRMD and MRMD bursts support
    • Request interleaving support
    • Supports 2-Dimensional block burst address sequences.
    • Compliance to phase-ordering rules.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV OCP VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure OCP Assertion IP functionality.

Benefits

  • Runs in every major formal and simulation environment.

Block Diagram

OCP Assertion IP Block Diagram

Deliverables

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

Request Info

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