NVDIMM-P Memory Model

Overview

NVDIMM-P Memory Model provides an smart way to verify the NVDIMM-P component of a SOC or a ASIC. The SmartDV's NVDIMM-P memory model is fully compliant with standard NVDIMM-P Specification and provides the following features. Better than Denali Memory Models.

NVDIMM-P Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

NVDIMM-P Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports NVDIMM-P memory devices from all leading vendors.
  • Supports 100% of NVDIMM-P protocol standard NVDIMM-P specifications.
  • Supports all the NVDIMM-P commands as per the specs.
  • Supports all Mode registers programming.
  • Supports programmable clock frequency of operation.
  • Supports Programmable burst lengths.
  • Supports Extend Command sets .
  • Supports Non-deterministic Read/Write latency support.
  • Supports RAS support.
  • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
  • Support all types of timing and protocol violation detection.
  • Constantly monitors NVDIMM-P behavior during simulation.
  • Protocol checker fully compliant with NVDIMM-P Specification.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster testbench development and more complete verification of NVDIMM-P designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

NVDIMM-P Memory Model
 Block Diagram

Deliverables

  • Complete regression suite containing all the NVDIMM-P testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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