Multiple Pixel Processing Camera Image Signal Processing Core

Overview

ASICFPGA HDR ISP core: The camera image signal processing core can be used in security camera, automotive camera, industrial camera and medical camera. Our camera image signal processing core produces high resolution, clear and sharp images by using intelligent and high-performance algorithm. The ISP core uses the minimum logic in spite of using the intelligent and complex algorithm. We can provide the core of the image size, speed, logic size and functions optimized at specific application. The ISP core is provided by Verilog source or FPGA netlist with the document and the testbench for developing FPGA and ASIC.

Key Features

Support RGB Bayer progressive image sensor and Monochrome progressive image sensor
Support 8 ~ 14 bit input data Bayer
Support image sensor of 256*256 ~ 8192*8192 size, including 4Kp60 and 4Kp120 at FPGA devices
Multiple pixel processing of 1, 2 or 4 pixels per clock
Support for AXI4-Lite and AXI4-Stream interfaces
Defect Correction
Lens Shading Correction
High quality interpolation
New Advanced 2D noise reduction and 3D Motion Adaptive noise reduction
Color correction by 3x3 matrix
Gamma correction
HDR processing for two or three Multiple exposure images and HDR bayer image
WDR (Shadow/Highlight compensation, back light compensation)
2D edge enhancement
Improved dynamic range with new AE of 17x15 windows and RGB Histograms
Improved White balance with new AWB of 128x96 windows and Color temperature detection
support Auto focus
Saturation, contrast and brightness control
Support special images (sepia, negative, solarization)

Multiple Pixel Processing Camera Image Signal Processing Core

Overview

Key Features

Block Diagram

Deliverables

Technical Specifications

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