Multi State Viterbi Decoder
Overview
The VA08V is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm. The decoder is designed for maximum flexibility, allowing it to decode various communications standards, as well as custom coding solutions.
Key Features
- 16, 32, 64 or 256 states (constraint length 5, 6, 7 or 9) Viterbi decoder
- Up to 692 MHz internal clock
- Up to 69 Mbit/s for 16, 32 or 64 states or 20 Mbit/s with 256 states
- Rate 1/2, 1/3, or 1/4 (inputs can be punctured for higher rates)
- 6-bit received signed magnitude data
- Optional block decoding with or without tail
- Estimated channel bit error outputs
- Optional serial or parallel data input
- Optional automatic synchronisation for rate 1/2 QPSK and rate 1/2 to 1/4 BPSK
- 965 6-input LUTs. 1, 2 or 4 18KB BlockRAMs.
- Asynchronous logic free design
- Free simulation software
- Available as EDIF and VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and Microsemi/Actel cores available on request.
Deliverables
- All Licenses
- EDIF Virtex-II, Spartan-3, Virtex-4 Core
- VHDL Virtex-5, Spartan-6, Virtex-6, 7-Series, UltraScale, UltraScale+ Core
- Test vector generator
- Channel simulation software
- ASIC License
- VHDL ASIC Core
- C++ bit/cycle exact simulation model
Technical Specifications
Availability
Now