The JDA1 is a digital-to-analog converter core cell suitable for all high quality audio multimedia applications. The JDA1 accepts a stereo digital PCM input signal at a standard sample rate (up to 24-bit resolution), and produces stereo analog outputs from that signal using a single master 27MHz clock, the same frequency as the system time clock (STC) of MPEG based systems. The baseline JDA1 is a fully digital Sigma-Delta converter that produces a pulsed output, which works in conjunction with a simple off-chip analog filter to provide the analog outputs. The JDA1 is applicable to switched-capacitor output filter circuitry as well, however the baseline configuration ismost applicable to large digital VLSI applications requiring audio outputs. Loop (PLL) to derive timing from the master clock.
A standard 3-wire serialPCM input interface allows I2S/EIAJ 24-bit digital audio signals to be fed to the JDA1. An S/PDIF transmitter allows formatting the input stereo PCM samples into the single-wire format used to send digital audio signals between audio products. This is programmable, allowing the sending of compressed data also, as specified by Dolby Labs for AC-3 signals. Finally, simple 3-wire or I2C microprocessor interfaces are available for allowing the setting of volume, muting, and other configuration bitsinside the JDA1 from a host processor.
The JDA1 is very efficient in silicon area, requiring only approximately 0.5mm2 in a standard 0.18u CMOS process. This includes logic gates and RAM necessary for the signal processing. No custom cell libraries are required. For ease in floorplanning, the JDA1 consists of only a single logic block plus one 1-port RAM. The JDA1 follows the Verilog/Synopsys design flow for easy porting to new libraries. For 96kHz applications, the JDA1 may be clocked at 54MHz. In this mode, the supported sample rates are 32, 44.1, 48, and 96kHz.
