Finite Impulse Response (FIR) filters are important building blocks in signal processing.
beam processing, diffraction compensation, equalisation and various signal processing applications. Many applications often involve filtering multiple data channels simultaneously, raising concerns about resource utilization. This design implements a multi-channel FIR filter (MFF) which allows multiple FIR filters to use the same hardware in a sequential manner, optimizing resource utilization. This MFF is a viable solution particularly suited for scenarios characterized by low data rates relative to the system clock.
In this design, data and coefficient widths, number of data channels and filter taps are all user selectable. All FIR filters have an identical number of taps. Filter taps can have the same or different values. MFF output width, as well as internal multiplier output width are also user selectable. This allows the user to optimize the filter outputs and resource utilization.
The MFF is implemented using VHDL and capable of being used on any FPGA/ASIC architecture.
Multi Channel FIR Filter
Overview
Key Features
- Multi Channel FIR filter
- Selectable data and coefficient widths
- Selectable number of data channels
- Selectable number of filter taps
- Selectable output width
- Selectable inner multiplier output width
- Resource sharing
- Fully synchronous design using only one clock
- Area/Power efficient RAM based architecture
- Coefficient read back available
- Low latency
- Multiple MFFs can be combined in parallel to form MFF banks
Block Diagram
Deliverables
- Synthesizable RTL source code in VHDL
- Comprehensive verification test bench and vectors in VHDL
- Integration documentation and user guide