MIPI Unipro v1.6 Controller IP, Compatible with M-PHY and UFS

Overview

UniPro (Unified Protocol) is a layered protocol defined by the MIPI Alliance for connecting devices and components within a mobile device. UniPro allows device components to utilize MIPI PHY layer to communicate and exchange data with devices on the other side of MIPI lanes. UniPro supports a wide range of device applications like application processor, camera controller, display controllers, and storage controllers like UFS or memory (RAM) controllers.
Our MIPI UniPro is designed to be PHY-agnostic, supporting a wide range of applications simultaneously in the application layer. Our MIPI UniPro along with other application solutions like CSI-3 or UFS and MPHY offers an comprehensive solution

Key Features

  • Compliant with MIPI UniPro Standard V1.6 and MPHY standard 3.x
  • Programmable 1, 2, or 4 data lanes
  • Support for M-PHY HS data rates HS-Gear-1, Gear-2, Gear-3, both A/B modes and PWM data rates PWM-G1 to PWM-G7
  • Support for end-to-end flow control
  • Support for all traffic classes
  • Support for preemption of high-priority frames
  • Support for up to 32 C-Ports
  • Round Robin arbitration across C-Ports
  • Group acknowledgement of up to 16 frames per traffic class
  • Support for frame retransmission
  • Configurable buffer spaces
  • CSD, CSV support
  • Support for UniPro test feature
  • TMPI support
  • Efficient power management

Benefits

  • Highly Modular and scalable design
  • Active-low
  • Asynchronous reset

Block Diagram

MIPI Unipro v1.6 Controller IP, Compatible with M-PHY and UFS  Block Diagram

Applications

  • IOT
  • Automotive
  • Storage
  • Consumer
  • Embedded
  • Enterprise

Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and
  • Performance monitors
  • Configurable synthesis shell
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Technical Specifications

Foundry, Node
Independent, suitable to all 3rd party PHY's
Maturity
In Production
Availability
Immediate
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Semiconductor IP