Our Universal Flash Storage (UFS) Controller IP is compliant with the latest JEDEC UFS v3.1 specification. The UFS standard is a high performance, low power serial interface that efficiently moves data between a host processor and mass storage devices. When our UFS Controller IP is combined with in-house developed UniPro Controller IP and M-PHY IP, designers can easily integrate PHY and the controller with low risk and accelerate time-to market with our UFS IP solution.
Verification :
IP Functionally is verified in NC – Verilog simulation software using test bench written in Verilog HDL
MIPI UFS v3.1 Host Controller IP, Compatible with M-PHY and Unipro
Overview
Key Features
- Compliant with the JEDEC UFS v3.1
- Backward compatibility JEDEC UFS v3.0 & v2.1
- TAG overlap/LBA overlap/Valid UPIU check
- Maximum DATA OUT = 64KB
- Maximum DATA IN = 64KB
- Maximum RTT number= 8
- CMD Queue Depth = 32
- HW Auto NOP IN Response
- HW Auto Query Response
- HW Auto Write Function
- Support HPB v1.0 (Host-aware Performance Booster)
- Support EHS (Extra Header Segment)
Benefits
- Write-protect options include permanent and power-on protection
- RMM-compliant synthesizable RTL design in Verilog
- Easy-to-use test environment
Block Diagram
Applications
- IOT
- Automotive
- Storage
- Consumer
- Embedded
- Enterprise
Deliverables
- User Manual
- Behavior model
- RTL codes
- Test patterns
- Test Documentation
Technical Specifications
Foundry, Node
Independent, suitable to all 3rd party PHY's
Maturity
In Production
Availability
Immediate
Related IPs
- UFS 3.1 Host Controller compatible with M-PHY 4.1 and UniPro 1.8
- UFS 4.0 Host Controller compatible with M-PHY 5.0 and UniPro 2.0
- UFS 2.1 Host Controller compatible with M-PHY 3.1 and UniPro 1.6
- MIPI UFS v3.1 Device Controller IP, Compatible with M-PHY and Unipro
- MIPI UFS v2.1 Host Controller IP, Compatible with M-PHY and Unipro
- UFS 3.0 Host Controller compatible with M-PHY 4.0 and UniPro 1.8