IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI Controller IP > MIPI SPMI IP > MIPI SPMI PSVIP

MIPI SPMI PSVIP

Overview

MIPI SPMI Post Silicon Validation IP (MIPI SPMI Protocol Analyzer And Exerciser) provides a smart way to post silicon validation of the MIPI SPMI component of a SOC. MIPI SPMI Post Silicon Validation IP provides an smart way to post silicon validation of the MIPI SPMI bi-directional two-wire bus. The SmartDV's MIPI SPMI Post Silicon Validation IP is fully compliant with version 2.0 MIPI Alliance specification for System Power Management Interface and provides the following features.

MIPI SPMI PSVIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI SPMI PSVIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports 1.0 and 2.0 MIPI SPMI Specification.
  • Supports Full MIPI SPMI Master and Slave functionality.
  • Operates as a Master, Slave, or both.
  • Supports all topologies as per the MIPI SPMI specification.
  • Supports multiple slaves and multiple masters.
  • Compares read data with expected results.
  • Support for slave requests through Alert bit.
  • Support for slave request hold.
  • Supports following master bus connecting on bus.
    • Connecting by detecting SSC
    • Connecting by detecting Bus idle
    • Connecting by detecting Bus arbiration
  • Supports following frames
    • Command Frame
    • Data/Address Frame
    • No Response Frame
  • Supports all types of SPMI commands.
  • Supports ACK/NACK generation as per 2.0 specs.
  • Supports various kind of Master and Slave errors generation.
    • Undefined command frame
    • Command frame with parity error
    • Command frame length error
    • Address frame with parity error
    • Data frame with parity error
    • Read of unused register
    • Write of an unused register
    • Read using the broadcast ID or a GSID
    • ACK/NACK errors
  • Supports extended register read/writes.
  • Supports optional signal also.
  • Supports device enumeration.
  • Supports master and slave arbitration.
  • Supports bus-accurate timing.
  • Supports programmable speed.

Benefits

  • Runs in custom FPGA platforms
  • Validate SPMI device for compliance

Block Diagram

MIPI SPMI PSVIP Block Diagram

Deliverables

  • Linux Perl Driver to control the PSVIP
  • Encrypted RTL of PSVIP or Bit file for selected FPGA platform
  • Complete regression suite containing all the MIPI SPMI testcases
  • Detailed documentation of all functions of perl driver and testcases
  • Documentation also contains User's Guide and Release notes

Technical Specifications

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